Experiments in Text-to-Verilog with ChatGPT-4o

5 min readAug 17, 2024

This post logs my experiments with ChatGPT-4o with regards to taking logic expressed in natural language and translating it to Verilog (Text-to-Verilog prompt completion). The examples are rudimentary in that I generate Verilog for a few very basic building-blocks.

The examples come from the highly rated Verilog by Example: A Concise Introduction for FPGA Design by Blaine C. Readler. Its also my first encounter with Verilog, I cannot guarantee the correctness of the generated output other than a rough cross-check against the author’s code.

Try them yourself! I haven’t tested whether the results are repeatable as Gen AI is hallucinatory, meaning the prompt will generate different outputs under the same conditions such as temperature and seed.

Simple in-out

As in the book, I start simply by expressing combinatorial AND and OR logic with three inputs two outputs.

Write a verilog function with three inputs and two outputs, 
the first output is a logical AND of all the inputs and 
the second output is a logical OR  of all the inputs.

Simple 4-bit Bus Multiplexor

Stating the multiplexor logic as simply as we can; when the control in_3 is high, select the 4-bit in_2, else select the 4-bit in_1.

Write verilog for the following:
Perform a combinatorial operation on two 4-bit input (in_1 and in_2) 
buses (aka vectors) and a single-bit (aka scalar) control signal (in_3). 
Essentially, when “in_3” is low, then “in_1” is selected, 
and when “in_3” is high, “in_2” is selected. 
Hint: This is of course a two input bus multiplexer.

Break-Combine Buses with Processing In-between

Below is our instructions, and we request bus concatenation operator, {}. Nice that it generates comments as well.

Write Verilog for the following: 
perform a concatenation operation giving out_1 in the following manner: 
- you have two inputs, in_1 and in_2, each is 4 bit. 
- the output has six bits
- bit 2 of in_1 is ANDed with bit 0 of in_2 and forms bit 2 of out_1 
- bit 3 of in_1 is ANDed with bit 1 of in_2 and forms bit 3 of out_1 
- the rest of the inputs directly go to the corresponding output.
- use bus concatenation to simplify the logic

A D-Flop Implemented with the always Block

Here, output out_1 follows input in_1 at the clocked edges.

write verilog 
- define a simple d-flop where the output follows the input at the 
positive edge
- the inputs are a clock and din_1 
- the output is out_1 
- add an asynchronous reset to our simple D-flop where "reset" 
forces "out_1" low immediately
- "out_1" then remains low until clocked again back high

More Combinatorial Logic…

Generate Verilog that ANDs input a and input b as an intermediate stage 
and then ANDs the intermediate output with input c to create output 1 
and ORs the intermediate output to input c to create output 2

Finally, a Finite State Machine

This description is paraphrased from the Verilog by Example book mentioned above.

Write Verilog for the finite state machine described below: 
— After receiving a “go” event, the state machine transitions from 
the “idle” state to the “active” state where it waits while an 
auxiliary counter steps through a one hundred clocks. Once this 
defined active duration is complete, the state machine returns to 
the “idle” state, but passes through one last “finish” state on the way. 
This “finish” state produces a one-clock pulse on the “done” output signal. 
Include a “done” register on the output to avoid combinatorial 
decode glitches. 
— An external “kill” signal can terminate the wait active duration, 
forcing the state machine back to idle. For the sake of stability, 
though, the state machine waits in an “abort” state until the kill 
signal goes back inactive. 
— Code must be readable by using Verilog parameters (constants) for 
the states instead of numeric values. 
— Always use a global reset line on the positive edge 
— Note that this design assumes that the inputs are synchronized 
to an input clock that drives the hardware design.